First of all, the terms “set-up time” and “hold time”, such as they are used below, will be explained with reference to a flip-flop.
FIG. 10 illustrates a flip-flop 57. The flip-flop comprises a data input D for a data signal d, an output Q for an output signal q and a clock input for a clock signal c. The data signal d is scanned as a function of the clock signal c and a corresponding value issued as the output signal q.
This is illustrated schematically in FIG. 11. FIG. 11 shows, by way of example, one possible time characteristic of the signals d, c and q, wherein t denotes time. The clock signal c is a periodic signal, wherein for each rising edge of the clock signal c, the flip-flop 57 from FIG. 10 scans the data signal d and issues the corresponding value of the data signal d with a given component-dependent delay as the output signal q. A scanning process of this type takes place, for example, at moment t0. In order to ensure correct scanning of the data signal d, it is necessary that the data signal d to be scanned is “valid” for a given period ts before the scanning moment t0 and for a given period th after the scanning moment t0, i.e., does not exhibit a signal change beyond a particular threshold. In the example shown in FIG. 11, this is the case, and after a given delay time after the moment t0 the scanned value of the data signal d is issued as a new value of the output signal q. If, on the other hand, the illustrated signal change of the data signal d were to take place within the period ts or within the period th, this might result in defective scanning and hence in a defective output signal q. The period ts will be referred to below as the set-up time, the period th as the hold time.
Although the set-up and hold times have been explained, in this case, using the example of a flip-flop, adherence to such set-up and hold times is generally necessary in the case of circuit paths in which a data signal is processed as a function of a clock signal.
Modern integrated circuits, for example digital VLSI (“very large-scale integration”) circuits, conventionally comprise a large number of circuit paths of this type, in which set-up and hold times have to be adhered to for correct functionality of the circuit.
In the design of such circuits, what is known as a timing analysis, in which adherence to the set-up and hold times is checked in a circuit design, is therefore carried out. The circuit is provided in the form of a machine-readable description, for example in the form of what is known as a NetList, and is checked by means of what is known as EDA (“Electronic Design Automation”) software.
Respective set-up and hold times, which are to be adhered to, may thus be specified for each circuit path to be checked, i.e., for example, for each flip-flop or other element comprising a clock input and a data input. These set-up and hold times may optionally be predefined as a function of conditions under which the circuit operates, for example as a function of a temperature of the circuit, as a function of a clock frequency of the circuit or as a function of applied voltages, wherein these parameters may influence the necessary set-up and hold times.
These set-up and hold times to be predefined must accordingly be selected such that these values guarantee functioning of the circuit irrespective of the actual subsequent use and the circumstances thereof. In particular, the values of the set-up and hold times for each circuit path must be selected such that the circuit still functions even if both the set-up time and the associated hold time are borderline.
According to an approach known from the prior art, the shortest possible set-up time and a correspondingly required hold time associated with this shortest possible set-up time are used for each circuit path. This is also known as the “worst case”. It should be noted that the set-up and hold times required for the correct operation of a circuit path are independent of each other, i.e. within given limits, a relatively short set-up time may be compensated by a relatively long hold time and vice versa.
Although these predefined values allow the maximum possible performance on paths that are critical with respect to the set-up time, to be realistically calculated, there is nevertheless the drawback that an excessively long hold time must be allowed for on paths in which even a relatively long set-up time would be possible, i.e. which are not borderline with respect to the set-up time. If this long hold time is not adhered to with an existing circuit design, additional delay members (buffers) have to be provided in the design of the circuit, in what is known as “hold time fixing”, i.e. in the correction of circuit paths in which the hold time is infringed. This requires additional chip area in the implementation of the corresponding circuit and is therefore expensive.
Similar problems occur if the shortest possible hold time and a corresponding set-up time (which is longer than in the preceding case) are specified in each case for the circuit paths. This is referred to as the “best case”.